1. Field of the Invention
The invention relates to a voltage generating circuit, and more particularly, to a bandgap voltage generating circuit with a low standby current.
2. Description of the Prior Art
In the field of IC design, an accurate voltage is often utilized. This accurate voltage, commonly known as the bandgap voltage, can compensate temperature and manufacturing process variations of the IC. In other words, the bandgap voltage is not influenced by temperature and differences in the manufacturing process. The bandgap voltage generating circuit usually operates with a voltage regulator to transform the bandgap voltage into another voltage level that can be utilized by circuits.
Generally speaking, the theory behind the bandgap voltage generating circuit is to add a voltage having a positive temperature coefficient to another voltage having a negative temperature coefficient such that a voltage not related to the temperature can be obtained. For example, assume that there is a voltage V1 having a positive temperature coefficient and a voltage V2 having a negative temperature coefficient. An appropriate constant M is selected to make V1+MV2=Vbg, where the voltage Vbg is the above-mentioned bandgap voltage, and is not dependent on temperature in most cases.
Please refer to FIG. 1, which is a diagram of a conventional bandgap voltage regulator 100. The bandgap voltage regulator 100 comprises a start-up circuit 110, a bandgap generating circuit 120, and a voltage regulator 130.
In the bandgap voltage generating circuit 120, the voltages of the nodes A and B in the zone 121 are the same. Therefore, the circuit of the zone 120 can be simplified as zone 122 to become the equivalent circuit shown in FIG. 2. Since the voltages of nodes A and B are equal, the zone 122 can also be seen as a loop. The current I3 flowing through the loop is generated by the voltage difference VBE1−VBE2 between the emitter and the base of the BJTs Q1 and Q2 and the resistor R1. In other words, the current I3 can be represented by the following equation:I3=(VBE1−VBE2)/R1  equation (1)
where VBE1=VT In (Ic1/Is), VBE2=VT In (Ic2/Is) such that the following equation can be obtained.
                                                                        I                3                            =                                                                    V                    T                                    ⁡                                      [                                                                  ln                        ⁡                                                  (                                                                                    Ic                              1                                                        /                                                          Is                              1                                                                                )                                                                    -                                              ln                        ⁡                                                  (                                                                                    Ic                              2                                                        /                                                          Is                              2                                                                                )                                                                                      ]                                                  /                                  R                  1                                                                                                        =                                                                    V                    T                                    ⁡                                      [                                          ln                      ⁡                                              (                        n                        )                                                              ]                                                  /                                  R                  1                                                                                        equation        ⁢                                  ⁢                  (          2          )                    
Please note that the value n, which is equal to (Ic1*Is2)/(Is1*Ic2), can be determined by the circuit designer. From the above equation (2), it can be seen that the current I3 is a current having a positive temperature coefficient. Referring to FIG. 1, the current I4 could be seen as a copy of current I3 by using a current mirror. Therefore, after passing through the resistor R2, the current I4 is transformed into a voltage having a positive temperature coefficient. This can be illustrated by the following equation:VR2=VT[In(n)]*(R2/R1)  equation (3)
Furthermore, from referring to chapter 4.4.3 of the textbook “Analysis and Design of Analog Integrated Circuits (4th Edition) by Paul R. Gray, et al”, the voltage difference VBE between the base and the emitter of the BJT can be represented by the following equation (4):VBE=Vbg−VT(a*InT−InK)  equation (4)
As Vbg, a, and K are all constants (meaning that they are not influenced by temperature), and VT and T are variables, which have positive temperature coefficients, the voltage difference VBE is a voltage having a negative temperature coefficient.
As the voltage level VC of node C is the sum of the voltage difference VBE3 and the voltage drop across the resistor R2, it can be represented by the following equation:
                                                                        V                C                            =                                                V                                      B                    ⁢                                                                                  ⁢                    E                    ⁢                                                                                  ⁢                    3                                                  +                                  V                                      R                    ⁢                                                                                  ⁢                    2                                                                                                                          =                                                V                                      b                    ⁢                                                                                  ⁢                    g                                                  -                                                      V                    T                                    ⁡                                      (                                                                                            a                          3                                                *                        ln                        ⁢                                                                                                  ⁢                        T                                            -                                              ln                        ⁢                                                                                                  ⁢                                                  K                          3                                                                                      )                                                  +                                                                            V                      T                                        ⁡                                          [                                              ln                        ⁡                                                  (                          n                          )                                                                    ]                                                        *                                      (                                                                  R                        2                                            /                                              R                        1                                                              )                                                                                                          equation        ⁢                                  ⁢                  (          5          )                    
Similarly, the circuit designer can define parameters of the above-mentioned devices (such as the transistors or the resistors) such that the voltage VC of node C can be equal to the bandgap voltage Vbg.
In addition, the conventional voltage regulator 130 comprises an operational amplifier 131 and a voltage dividing circuit 132. The voltage regulator 130 can generate a regulated voltage at the node D according to the above-mentioned bandgap voltage Vbg at the node C. The voltage dividing circuit 132 can divide the regulated voltage to generate a divided voltage at the node E. The divided voltage is fed back to the input end of the operational amplifier 131. Therefore, the operational amplifier 131 generates the regulated voltage according to the fed back divided voltage and the bandgap voltage Vbg. In the same way, the circuit designer can adjust the resistance of the resistors R4 and R3 such that an appropriate voltage can be generated to be used by the core circuit 140.
The detailed architecture of the start-up circuit 110 is shown in FIG. 1. The start-up circuit 110 is to allow the bandgap voltage generating circuit 120 to work normally. The detailed operation of the start-up circuit 110 is well known, and thus omitted here.
Although the above-mentioned bandgap voltage regulator 100 provides a relatively accurate regulated voltage, the bandgap voltage regulator 100 consumes currents I0˜I5 in addition to the operating current of the operational amplifier 131. Even during the time when the core circuit 140 is in standby mode, regulated voltage is still provided by the bandgap voltage regulator 100 such that the core circuit 140 can successfully switch itself from standby mode into active mode. The large power consumption of the currents will thus reduce the life expectancy of circuit power supplies of electronic appliances.